Fig. 7

Timing chart for signal processing with VATA460.3. Readout sequence begins with trigger signal from ASICs in first SSD layer. The CONTROL board inputs a sample/hold signal to all ASICs after a defined delay from the trigger signal. The CONTROL board supplies the ADC clocks and receives a signal from the ASICs when the conversion is finished. After receiving confirmation from all ASICs that the A/D conversion has completed, the CONTROL board supplies the ASICs readout clock. After reading out all the data, the CONTROL board resets the digital part of the ASICs and waits for the next trigger signal